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dc.contributor.authorYurdakul, Arda
dc.date.accessioned2019-06-28T11:12:00Z
dc.date.available2019-06-28T11:12:00Z
dc.date.issued2000
dc.identifier.issn2714310
dc.identifier.urihttps://hdl.handle.net/20.500.12469/1754
dc.identifier.urihttps://doi.org/10.1109/ISCAS.2000.858690
dc.description.abstractIn this study a synthesis tool using a novel multirate folding technique which handles each FIR filter in a multirate DSP system as a single node is developed. A new architecture is presented for the multiplierless realization of a fold of multirate FIR filters. This synthesizer fully exploits the redundancies (i.e. `idle' and `missing' cycles) and common terms in multirate systems without sacrificing from overall system quality to produce multiplierless multirate systems. It also enables the usage of a single clock for all parts of the circuit.
dc.language.isoEnglish
dc.publisherIEEE
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.titleA synthesis tool for the multiplierless realization of FIR-based multirate DSP systems
dc.typeConference Paper
dc.identifier.startpageIV-69
dc.identifier.endpageIV-72
dc.relation.journal2000 IEEE International Symposium on Circuits and Systems (ISCAS)
dc.identifier.volume4
dc.identifier.doi10.1109/ISCAS.2000.858690
dc.contributor.khasauthorYurdakul, Arda


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