Browsing by Author "Ahmadpour, Seyed-Sajad"

Now showing 1 - 18 of 18

Citation - WoS: 13
Citation - Scopus: 13
A Cost- and Energy-Efficient Sram Design Based on a New 5 I-P Majority Gate in Qca Nanotechnology
(Elsevier, 2024) Kassa, Sankit; Jafari Navimipour, Nima; Ahmadpour, Seyed-Sajad; Lamba, Vijay; Misra, Neeraj Kumar; Navimipour, Nima Jafari; Kotecha, Ketan
Quantum-dot Cellular Automata (QCA) is a revolutionary paradigm in the Nano-scale VLSI market with the potential to replace the traditional Complementary Metal Oxide Semiconductor system. To demonstrate its usefulness, this article provides a QCA-based innovation structure comprising a 5-input (i-p) Majority Gate, which is one of the basic gates in QCA, and a Static Random Access Memory (SRAM) cell with set and reset functionalities. The suggested design, with nominal clock zones, provides a reliable, compact, efficient, and durable configuration that helps achieve the optimal size and latency while decreasing power consumption. Based on the suggested 5 i-p majority gate, the realized SRAM architecture improves energy dissipation by 33.95 %, cell count by 31.34 %, and area by 33.33 % when compared to the most recent design designs. Both the time and the cost have been decreased by 30 % and 53.95 %, respectively.
Citation - WoS: 11
Citation - Scopus: 11
Cost-Effective Synthesis of Qca Logic Circuit Using Genetic Algorithm
(Springer, 2023) Pramanik, Amit Kumar; Mahalat, Mahabub Hasan; Pal, Jayanta; Ahmadpour, Seyed-Sajad; Sen, Bibhash
Quantum-dot cellular automata (QCA) is a field coupling nano-technology that has drawn significant attention for its low power consumption, low area overhead, and achieving a high speed over the CMOS technology. Majority Voter (MV) and QCA Inverter (INV) are the primitive logic in QCA for implementing any QCA circuit. The performance and cost of a QCA circuit directly depend on the number of QCA primitives and their interconnections. Their optimization plays a crucial role in optimizing the QCA logic circuit synthesis. None of the previous works considered elitism in GA, all the optimization objectives (MV, INV and Level), and the redundancy elimination approach. These profound issues lead us to propose a new methodology based on Genetic algorithm (GA) for the cost-effective synthesis of the QCA circuit of the multi-output boolean functions with an arbitrary number of inputs. The proposed method reduces the delay and gate count, where the worst-case delay is minimized in terms of the level. This methodology adapts elitism to preserve the best solutions throughout the intermediate generations. Here, MV, INV, and levels are optimized according to their relative cost factor in a QCA circuit. Moreover, new methodologies are proposed to create the initial population, maintain the variations, and eliminate redundant gates. Simulation results endorse the superiority of the proposed method.
Citation - WoS: 6
Citation - Scopus: 8
Design and Implementation of a Nano-Scale High-Speed Multiplier for Signal Processing Applications
(Elsevier, 2024) Ahmadpour, Seyed-Sajad; Kerestecioğlu, Feza; Jafari Navimipour, Nima; Ul Ain, Noor; Kerestecioglu, Feza; Yalcin, Senay; Avval, Danial Bakhshayeshi; Hosseinzadeh, Mehdi
Digital signal processing (DSP) is an engineering field involved with increasing the precision and dependability of digital communications and mathematical processes, including equalization, modulation, demodulation, compression, and decompression, which can be used to produce a signal of the highest caliber. To execute vital tasks in DSP, an essential electronic circuit such as a multiplier plays an important role, continually performing tasks such as the multiplication of two binary numbers. Multiplier is a crucial component utilized to implement a wide range of DSP tasks, including convolution, Fourier transform, discrete wavelet transforms (DWT), filtering and dithering, multimedia information processing, and more. A multiplier device includes a clock and reset buttons for more flexible operational control. Each digital signal processor constitutes a multiplier unit. A multiplier unit functions entirely autonomously from the central processing unit (CPU); consequently, the CPU is burdened with a significantly reduced amount of work. Since DSP algorithms must constantly carry out multiplication tasks, the employment of a high-speed multiplier to execute fast-speed filtering processes is vital. The previous multipliers had lots of weaknesses, such as high energy, low speed, and high area, because they implemented this necessary circuit based on traditional technology such as complementary metal-oxide semiconductor (CMOS) and very large-scale integration (VLSI). To solve all previous drawbacks in this necessary circuit, we can use nanotechnology, which directly affects the performance of the multiplier and can overcome all previous issues. One of the alternative nanotechnologies that can be used for designing digital circuits is quantum dot cellular automata, which is high speed, low area, and low power. Therefore, this manuscript suggests a quantum technology-based multiplier for DSP applications. In addition, some vital circuits, such as half adder, full adder, and ripple carry adder (RCA), are suggested for designing a multiplier. Moreover, a systolic array, accumulator, and multiply and accumulate (MAC) unit are proposed based on the quantum technologybased multiplier. Nonetheless, each of the suggested frameworks has a coplanar configuration without rotated cells. The suggested structure is developed and verified utilizing the QCADesigner 2.0.3 tools. The findings showed that all circuits have no complicated configuration, including a higher number of quantum cells, latency, and an optimum area.
Citation - WoS: 15
Citation - Scopus: 16
An efficient and energy-aware design of a novel nano-scale reversible adder using a quantum-based platform
(Elsevier, 2022) Jafari Navimipour, Nima; Navimipour, Nima Jafari; Mosleh, Mohammad; Bahar, Ali Newaz; Das, Jadav Chandra; De, Debashis; Yalcin, Senay
Quantum-dot cellular automata (QCA) is a domain coupling nano-technology that has drawn significant attention for less power consumption, area, and design overhead. It is able to achieve a high speed over the CMOS technology. Recently, the tendency to design reversible circuits has been expanding because of the reduction in energy dissipation. Hence, the QCA is a crucial candidate for reversible circuits in nano-technology. On the other hand, the addition operator is also considered one of the primary operations in digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, full-adders have become popular and extensively solve mathematical problems more efficiently and faster. They are one of the essential fundamental circuits in most digital processing circuits. Therefore, this article first suggests a novel reversible block called the RF-adder block. Then, an effective reversible adder design is proposed using the recommended reversible RF-adder block. The QCAPro and QCADesigner 2.0.3 tools were employed to assess the effectiveness of the suggested reversible full-adder. The outcomes of energy dissipation for the proposed circuit compared to the best previous structure at three different tunneling energy levels indicate a reduction in the power consumption by 45.55%, 38.82%, and 34.62%, respectively. (C) 2022 Elsevier B.V. All rights reserved.
Citation - WoS: 4
An Efficient Architecture of Adder Using Fault-Tolerant Majority Gate Based on Atomic Silicon Nanotechnology
(Ieee-inst Electrical Electronics Engineers inc, 2023) Jafari Navimipour, Nima; Jafari Navimipour, Nima; Bahar, Ali Newaz; Yalcin, Senay
It is expected that Complementary Metal Oxide Semiconductor (CMOS) implementation with ever-smaller transistors will soon face significant issues such as device density, power consumption, and performance due to the requirement for challenging fabrication processes. Therefore, a new and promising computation paradigm, nanotechnology, can replace CMOS technology. In addition, a new frontier in computing is opened up by nanotechnology called atomic silicon, which has the same extraordinary behavior as quantum dots. On the other hand, atomic silicon circuits are highly prone to defects, so suggested fault-tolerant structures in this technology play important roles. The full adders have gained popularity and find widespread use in efficiently solving mathematical problems. In the following article, we will explore the development of an efficient fault-tolerant 3-input majority gate (FT-MV3) using DBs, further enhancing the capabilities of digital circuits. A rule-based approach to the redundant DB achieves a less complex and more robust atomic silicon layout for the MV3. We use the SiQAD tool to simulate proposed circuits. In addition, to confirm the efficiency of the proposed gate, all common defects, such as single and double dangling bond omission defects and DB dislocation defects, are examined. The suggested gate is 100% and 66.66% tolerant against single and double DB omission defects, respectively. Furthermore, a new adder design is introduced using the suggested FT-MV3 gate. The results show that the suggested adder is 44.44% and 35.35% tolerant against single and double DB omission defects. Finally, a fault-tolerant four-bit adder is designed based on the proposed adder.
Citation - WoS: 27
Citation - Scopus: 29
An Efficient Design of Multiplier for Using in Nano-Scale Iot Systems Using Atomic Silicon
(IEEE-Inst Electrical Electronics Engineers Inc, 2023) Ahmadpour, Seyed-Sajad; Jafari Navimipour, Nima; Heidari, Arash; Navimpour, Nima Jafari; Asadi, Mohammad-Ali; Yalcin, Senay
Because of recent technological developments, such as Internet of Things (IoT) devices, power consumption has become a major issue. Atomic silicon quantum dot (ASiQD) is one of the most impressive technologies for developing low-power processing circuits, which are critical for efficient transmission and power management in micro IoT devices. On the other hand, multipliers are essential computational circuits used in a wide range of digital circuits. Therefore, the multiplier design with a low occupied area and low energy consumption is the most critical expected goal in designing any micro IoT circuits. This article introduces a low-power atomic silicon-based multiplier circuit for effective power management in the micro IoT. Based on this design, a $4\times 4$ -bit multiplier array with low power consumption and size is presented. The suggested circuit is also designed and validated using the SiQAD simulation tool. The proposed ASiQD-based circuit significantly reduces energy consumption and area consumed in the micro IoT compared to most recent designs.
Citation - WoS: 12
Citation - Scopus: 13
An Energy-Aware Nanoscale Design of Reversible Atomic Silicon Based on Miller Algorithm
(IEEE-Inst Electrical Electronics Engineers Inc, 2023) Jafari Navimipour, Nima; Jafari Navimipour, Nima; Bahar, Ali Nawaz; Mosleh, Mohammad; Yalcin, Senay
Area overhead and energy consumption continue to dominate the scalability issues of modern digital circuits. In this context, atomic silicon and reversible logic have emerged as suitable alternatives to address both issues. In this article, the authors propose novel nano-scale circuit design with low area and energy overheads using the same. In particular, the authors propose a reversible gate with Miller algorithm and atomic silicon technology. This article is extremely relevant in todays era, when the world is moving toward low area and low energy circuits for use in edge devices.
Citation - WoS: 12
Citation - Scopus: 9
A Nano-Scale Arithmetic and Logic Unit Using a Reversible Logic and Quantum-Dots
(Springer, 2023) Navimipour, Nima Jafari; Jafari Navimipour, Nima; Ahmadpour, Seyed-Sajad; Yalcin, Senay
The arithmetic and logic unit (ALU) is a key element of complex circuits and an intrinsic part of the most widely recognized complex circuits in digital signal processing. Also, recent attention has been brought to reversible logic and quantum-dot cellular automata (QCA) because of their intrinsic capacity to decrease energy dissipation, which is a crucial need for low-power digital circuits. QCA will be the preferred technology for developing the subsequent generation of digital systems. These technologies played a substantial role in the design of the ALU for operations such as multiplication, subtraction, and division. In developing reversible logic and QCA technologies, the ALU is frequently studied as a central unit. Implementing an efficient ALU with low quantum cost and a small number of cells based on an efficient reversible block can solve all previous issues. Therefore, this research constructs a Feynman gate, a Fredkin gate, and full adder circuits using reversible logic and QCA technology. Using all of the specified circuits, a 20-operation ALU is constructed. The power consumption of the proposed ALU under various energy ranges demonstrated significant improvements over earlier designs.
Citation - WoS: 12
Citation - Scopus: 12
A Nano-Scale Design of a Multiply-Accumulate Unit for Digital Signal Processing Based on Quantum Computing
(Springer, 2024) Ahmadpour, Seyed-Sajad; Jafari Navimipour, Nima; Navimipour, Nima Jafari; Yalcin, Senay; Bakhshayeshi Avval, Danial; Ul Ain, Noor
Digital signal processing (DSP) is used in computer processing to conduct different signal-processing tasks. The DSPs are used in the series numbers representing a continuous variable in a domain such as time, area, or frequency. The multiply-accumulate (MAC) unit is crucial in various DSP applications, including convolution, discrete cosine transform (DCT), Fourier Transform, etc. Thus, all DSPs contain a critical MAC unit in signal processing. The MAC unit conducts multiplication and accumulation operations for continuous and complicated DSP application processes. On the other hand, in the MAC structure, the stability of the circuit and the occupied area pose some significant challenges. However, high-performance quantum technology can easily overcome all the previous shortcomings. Hence, this paper suggests an efficient MAC for DSP applications using a Vedic multiplier, half adder, and accumulator based on quantum technology. All the proposed structures have used a single-layer layout without rotated cells. The suggested architecture is designed and validated based on the QCADesigner 2.0.3 tool. The findings revealed that all the developed circuits have a simple architecture with fewer quantum cells, optimal area, and low latency.
Citation - WoS: 30
Citation - Scopus: 35
A Nano-Scale N-Bit Ripple Carry Adder Using an Optimized Xor Gate and Quantum-Dots Technology With Diminished Cells and Power Dissipation
(Elsevier, 2023) Ahmadpour, Seyed-Sajad; Jafari Navimipour, Nima; Navimipour, Nima Jafari; Mosleh, Mohammad; Bahar, Ali Newaz; Yalcin, Senay
In the nano-scale era, quantum-dot cellular automata (QCA) technology has become an appealing substitute for transistor-based technologies. QCA will be the preferred technology for developing the next generation of digital systems. On the other hand, the full-adder and ripple carry adder (RCA) are the crucial building blocks of complex circuits, the most used structures in digital operations systems, and a practical part of the most well-known complex circuits in QCA technology. In addition, this technology was used to design the full adder for several procedures, like multiplication, subtraction, and division. For this reason, the full adder is generally investigated as a central unit and microprocessor in developing QCA technology. Furthermore, most previous QCA-based adder structures have suffered from some drawbacks, such as a high number of cells, high energy consumption, the high number of gates, and the placement of inputs and outputs in a closed loop; hence, the implementation of an efficient adder with only one gate and a low number of cells, such as exclusive-OR (XOR) gate, can solve all previous problems. Therefore, in this paper, a significantly improved structure of 3-input XOR is suggested based on the promising QCA technology. In addition, a QCA clocking mechanism and explicit cell interaction form the foundation of the proposed QCA-based XOR gate configuration. This gate can be easily converted into an adder circuit while containing a small number of cells and being extremely compressed. The suggested QCA-based XOR design is focused on optimizing a single-bit adder using cellular interaction. The suggested single-bit adder contains 14 cells. Based on this adder, several different RCAs, such as 4, 8, 16, and 32-bit, are designed. The comparison of the proposed single-bit adder to the best coplanar and multi-layer ones shows a 51.72% and 36.36% reduction of cells, respectively. In addition, all suggested designs are verified through simulation using QCADesigner and QCAPro. Finally, many physical validations are provided to approve the functionality of the suggested XOR design.(c) 2023 Elsevier B.V. All rights reserved.
Citation - WoS: 7
Citation - Scopus: 6
A New Design of a Digital Filter for an Efficient Field Programmable Gate Array Using Quantum Dot Technology
(Elsevier, 2024) Taghavirashidizadeh, Ali; Jafari Navimipour, Nima; Ahmadpour, Seyed-Sajad; Ahmed, Suhaib; Navimipour, Nima Jafari; Kassa, Sankit Ramkrishna; Yalcin, Senay
Digital filtering algorithms are most frequently used to implement generic-based Field-programmable gate arrays (FPGAs) chips, which are used for higher sampling rates. In the filtering structure, delay and occupied areas play a vital role. Since the existing structures suffered from shortcomings such as high delay and high occupied area, implementing a high-performance digital filter circuit with high speed and low occupied area based on unique technology can significantly improve the performance of whole FPGA structures. One of the best technologies to implement this vital structure to solve these shortcomings is quantum-dot cellular automata (QCA) technology. This paper presents several new efficient full adders for digital filter applications based on quantum technology, including a multiplier, AND gate, and accumulator. The QCADesigner 2.0.3 tool is used to create and validate the suggested designs. According to the results, all designed circuits have simple structures with few quantum cells, low area, and low latency.
Citation - WoS: 16
Citation - Scopus: 21
A New Design of Parity Preserving Reversible Vedic Multiplier Targeting Emerging Quantum Circuits
(Wiley, 2023) Noorallahzadeh, Mojtaba; Mosleh, Mohammad; Ahmadpour, Seyed-Sajad; Pal, Jayanta; Sen, Bibhash
Reversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, Vedic mathematics, as a set of techniques sutras, has become popular and is extensively used to solve mathematical problems more efficiently and faster. This work proposes three PP reversible blocks, N-1, N-2, and N-3, which are used to develop a novel effective 2-bit PP reversible Vedic multiplier and 4-bit ripples carry adders (RCAs). Moreover, 2-bit Vedic multiplier and RCA are used to develop the 4-bit PP reversible Vedic multiplier. The proposed designs outperform the most relevant state-of-the-art structures in terms of garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Average savings of 22.37%, 35.44%, 35.44%, and 34.76%, and 17.76%, 26.60%, 24.52%, and 27.27% respectively, are observed for two-bit and four-bit PP reversible Vedic multipliers in terms of QC, GO, CI and GC as compared to previous works.
Citation - WoS: 12
Citation - Scopus: 13
A New Energy-Efficient Design for Quantum-Based Multiplier for Nano-Scale Devices in Internet of Things
(Pergamon-elsevier Science Ltd, 2024) Ahmadpour, Seyed-Sajad; Jafari Navimipour, Nima; Noorallahzadeh, Mojtaba; Al-Khafaji, Hamza Mohammed Ridha; Darbandi, Mehdi; Navimipour, Nima Jafari; Javadi, Bahman; Yalcin, Senay
An enormous variety of items and things are connected via wired or wireless connections and specific addressing schemes, which is known as the Internet of Things (IoT). However, IoT devices that adopt aggressive duty-cycling for high power efficiency and prolonged lifespan necessitate the incorporation of ultra-low power consumption always-on blocks. The multiplier plays a crucial role in enhancing the capabilities of low-power IoT devices, particularly those operating with energy-efficient batteries that offer extended battery life. The previous multipliers have a struggling speed, enormous occupied area, and high energy consumption; therefore, all prior flaws must be fixed by implementing it in a suitable technology, like the quantum computing. Therefore, this paper examines the ultra-low power circuit for nano-scale IoT platforms. It also suggests novel quantum-based adders for multiplier structure. The proposed designs are simulated using the QCADesignerE 2.2 tool by focusing on energy-efficient and occupied areas for miniaturizing IoT systems.
Citation - WoS: 10
Citation - Scopus: 9
A New Nano-Design of 16-Bit Carry Look-Ahead Adder Based on Quantum Technology
(Iop Publishing Ltd, 2023) Ahmadpour, Seyed-Sajad; Jafari Navimipour, Nima; Navimipour, Nima Jafari
There is a requirement and a desire to develop reliable and energy-efficient circuit designs that adapt to the expanding field of low-power circuit engineering in the VLSI domain based on nanotechnology. The quantum-dot cellular automata (QCA) technology possesses the potential to supplant the conventional, complementary metal-oxide-semiconductor (CMOS) technology in low-power nano-scale applications due to its diminutive cell dimensions, dependable circuitry architecture, and robust structural integrity. On the other hand, the carry look-ahead adder (CLA) is one of the vital circuits in digital processing utilized in diverse digital applications. In addition, for the design of this essential circuit, the occupied area and the delay play the primary role because using a simple formulation can reduce the occupied area, energy consumption, and the number of gates count. In the previous structures, high delay and use of traditional technology (like CMOS) caused an increase in the number of gate counts and occupied areas. Using QCA technology, simple quantum cells, and a low delay, all the previous shortcomings can be resolved to reduce the number of gate counts and low occupied area in the CLA circuit. This paper proposes a new method that helps the propagation characteristics generate suitable signals to reduce the number of gate counts based on adders in QCA technology. Several new blocks are used to design fast binary adders. Finally, an optimal four and 16-bit CLA circuit will be proposed based on the adder circuit. Furthermore, the execution and experimentation of outcomes are carried out utilizing QCADesigner-2.0.3. The simulation-based comparison of values justified the proposed design's accuracy and efficiency. The simulation results demonstrate that the proposed circuit has a low area and quantum cell.
Citation - WoS: 0
Retraction: a Nano-Scale Design of a Multiply-Accumulate Unit for Digital Signal Processing Based on Quantum Computing
(Springer, 2024) Ahmadpour, Seyed-Sajad; Jafari Navimipour, Nima; Navimipour, Nima Jafari; Yalcin, Senay; Avval, Danial Bakhshayeshi; Ul Ain, Noor
[No Abstract Available]
Citation - WoS: 1
Citation - Scopus: 1
Secure Quantum-Based Adder Design for Protecting Machine Learning Systems Against Side-Channel Attacks
(Elsevier, 2025) Jafari Navimipour, Nima; Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Diakina, E.; Kassa, Sankit R.
Machine learning (ML) has recently been adopted in various application domains. Usually, a well-performing ML model relies on a large volume of training data and powerful computational resources. Recently, hardware accelerators utilizing field programmable gate arrays (FPGAs) have been developed to provide high-performance hardware while maintaining the required accuracy for ML tools. However, one of the main challenges hindering the FPGA-based ML models is their susceptibility to adversarial attacks, such as physical side-channel attacks. In this study, various kinds of countermeasures, including masking and hiding techniques, are examined to mitigate the aforementioned shortcomings and enhance the security of FPGA-based ML systems. In addition to FPGA-based defenses, the advantages of quantum computing for designing circuits to enhance data protection are also elaborated. However, concerning FPGA-based ML models, which are used to defend against physical side-channel attacks, quantum dot cellular automata (QCA) offers a more promising option. Its inherent security, lower power consumption, higher speed, and reduced vulnerability to side-channel leakage make it the best alternative. Therefore, this study emphasizes the implementation of the quantum nature of QCA to protect valuable information against physical side-channel attacks. It also offers quantum masking circuits for protecting sensitive information in machine learning systems, including XOR, adder, and RCA. Furthermore, the presented work advocates for leveraging QCA technology to augment the security of machine learning systems by mitigating the disclosure of sensitive data. The proposed QCA-based masked designs, which include an adder and a ripple carry adder (RCA), pose some qualities, which include a single-layer structure, minimal cell count, and low latency. When compared with the best counterparts among the recommended designs, these designs exhibit significant improvements regarding cell consumption and occupied area, with improvements of 33.3% and 36.6% respectively.
Citation - WoS: 17
Citation - Scopus: 18
Toward implementing robust quantum logic circuits using effectual fault-tolerant majority voter gate
(Elsevier, 2024) Jafari Navimipour, Nima; Mosleh, Mohammad; Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Shahrbanoonezhad, Alireza
Quantum -dot Cellular Automata (QCA) has emerged as a revolutionary technology for nano-scale computing circuits and a promising alternative to conventional transistor-based technologies. However, the susceptibility to defects during circuit synthesis is a pivotal challenge, undermining its potential. This study seeks to introduce an innovative and robust fault-tolerant 3 -input majority voter gate comprising 16 simple cells. The primary objective is to enhance the gate's resilience against two specific defects: one-cell omission and extra-cell deposition. Preliminary assessments indicate that the introduced gate achieves remarkable tolerance rates of 100% for one-cell omission and 89.47% for extra-cell deposition defects. A comprehensive evaluation is used based on the QCADesigner 2.0.3 simulator to validate the gate's performance, supplemented by physical proofs. Furthermore, leveraging the novel gate structure, this paper extends its application to the design of fault-tolerant flip-flops and multiplexer circuits. These building blocks are then employed to construct three distinct fault-tolerant sequential circuits.
Citation - WoS: 3
Citation - Scopus: 4
An Ultra-Efficient Design of Fault-Tolerant 3-Input Majority Gate (ftmg) With an Error Probability Model Based on Quantum-Dots
(Pergamon-Elsevier Science Ltd, 2023) Ahmadpour, Seyed-Sajad; Jafari Navimipour, Nima; Navimipour, Nima Jafari; Kassa, Sankit; Misra, Neeraj Kumar; Yalcin, Senay
Quantum-dot cellular automata (QCA) has recently attracted significant notice thanks to their inherent ability to decrease energy dissipation and decreasing area, which is the primary need of digital circuits. However, the lack of resistance of QCA circuits under defects in previous works is a vital challenge affecting the stability of the circuit and output production. In addition, with the high defect rate in QCA, suggesting resistance and stable structures is critical. Furthermore, the 3input majority gate is a fundamental component of QCA circuits; therefore, improving this essential gate would enable the development of fault-tolerant circuits. This paper recommends a 3-input majority gate which is 100% fault-tolerant against single-cell omission defects. Moreover, the fundamental gates are introduced based on the proposed gate. In addition, an adder and a 1:2 decoder are also designed. Using QCADesigner 2.0.3 and QCAPro software, simulations of structures and analysis of power consumption are performed.