Browsing by Author "Navimipour,N.J."
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Book Part Citation Count: 4Cloud-based non-destructive characterization(Elsevier, 2023) Heidari,A.; Navimipour,N.J.; Otsuki,A.Cloud services have grown in popularity; businesses, organizations, industries, and academic institutions use cloud services such as Cloud Non-destructive Characterization Testing (CNDCT), also known as Cloud Testing (CT). Vendors compete to deliver highly reliable services, diverse requirements, and product qualities. The CT platforms can test cloud-based systems or use the cloud for testing purposes: both approaches have sparked interest in the research. Cloud testing draws many companies and sectors worldwide by offering potential solutions for managing software applications and providing convenient testing environments. Because of cloud computing, Testing as a Service (TaaS) was born. Given the capabilities of TaaS, it has created several issues and obstacles, particularly in cloud-based, non-destructive testing environments. So, this chapter reviews and addresses the obstacles and benefits of CNDCT, including a theoretical comparison between the cloud-based testing environment and traditional standard system testing. © 2024 Elsevier Inc. All rights reserved.Conference Object Citation Count: 1A New Nano-Design of an Efficient Synchronous Full-Adder/Subtractor Based on Quantum-Dots(ISRES Publishing, 2023) Kerestecioğlu, Feza; Navimipour,N.J.; Kerestecioglu,F.Quantum-dot cellular automata (QCA), known as one of the alternative technologies of CMOS technology, promises to design digital circuits with extra low-power, extremely dense, and high-speed structures. Moreover, the next generation of digital systems will be used QCA as desired technology. In designing arithmetic circuits, efficient designs such as full-adder and full-subtractor can play a significant role. In addition, they are considering the most used structures in digital operations. Furthermore, full-adder and fullsubtractor are always effective parts of all complex and well-known circuits such as Arithmetic Logic Unit (ALU), Microprocessors, etc. This paper proposes low complexity and high-speed QCA coplanar synchronous full-adder/subtractor structures by applying formulations based on the Exclusive-OR gate to decrease energy consumption. The proposed design is simulated using QCADesigner 2.0.3. The simulation results confirm the efficiency of the proposed circuit. Moreover, comparative investigation indicates the superiority of proposed designs compared to state-of-the-art designs. Finally, the suggested QCA coplanar synchronous fulladder/subtractor shows 5.88% and 7.69% improvement in consumed cells relative to the best full adder and full subtractor, respectively. © 2023 Published by ISRES.Article Citation Count: 0Towards Atomic Scale Quantum Dots in Silicon: An Ultra-Efficient and Robust Subtractor using Proposed P-shaped Pattern(Institute of Electrical and Electronics Engineers Inc., 2024) Rasmi,H.; Mosleh,M.; Navimipour,N.J.; Kheyrandish,M.Today, Complementary Metal-OxideSemiconductor (CMOS) technology faces critical challenges, such as power consumption and current leakage at the nanoscale. Therefore, Atomic Silicon Dangling Bond (ASDB) technology has been proposed as one of the best candidates to replace CMOS technology; due to its high-speed switching and low power consumption. Among the most important issues in ASDB nanotechnology, output stability and robustness against possible faults may be focused. This paper first introduces a novel P-shaped pattern in ASDB, for designing stable and robust primitive logic gates, including AND, NAND, OR, NOR and XOR. Then, two combinational circuits, half-subtractor and full-subtractor, are proposed by the proposed ASDB gates. The simulation results show high output stability as well as adequate robustness, against various defects obtained by the proposed designs; on average, they have improvements of more than 56% and 62%, against DB omission defects and extra cell deposition defects; respectively. Also, the results of the investigations show that the proposed circuits have been improved by 65%, 21% and 2%, in terms of occupied area, energy and occurrence, respectively; compared to the previous works. IEEE