Browsing by Author "Navimipour,N.J."

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Citation Count: 4
Cloud-based non-destructive characterization
(Elsevier, 2023) Heidari,A.; Navimipour,N.J.; Otsuki,A.
Cloud services have grown in popularity; businesses, organizations, industries, and academic institutions use cloud services such as Cloud Non-destructive Characterization Testing (CNDCT), also known as Cloud Testing (CT). Vendors compete to deliver highly reliable services, diverse requirements, and product qualities. The CT platforms can test cloud-based systems or use the cloud for testing purposes: both approaches have sparked interest in the research. Cloud testing draws many companies and sectors worldwide by offering potential solutions for managing software applications and providing convenient testing environments. Because of cloud computing, Testing as a Service (TaaS) was born. Given the capabilities of TaaS, it has created several issues and obstacles, particularly in cloud-based, non-destructive testing environments. So, this chapter reviews and addresses the obstacles and benefits of CNDCT, including a theoretical comparison between the cloud-based testing environment and traditional standard system testing. © 2024 Elsevier Inc. All rights reserved.
Citation Count: 0
Design and implementation of a nano-scale high-speed multiplier for signal processing applications
(Elsevier B.V., 2024) Kerestecioğlu, Feza; Navimipour,N.J.; Ain,N.U.; Kerestecioglu,F.; Yalcin,S.; Avval,D.B.; Hosseinzadeh,M.
Digital signal processing (DSP) is an engineering field involved with increasing the precision and dependability of digital communications and mathematical processes, including equalization, modulation, demodulation, compression, and decompression, which can be used to produce a signal of the highest caliber. To execute vital tasks in DSP, an essential electronic circuit such as a multiplier plays an important role, continually performing tasks such as the multiplication of two binary numbers. Multiplier is a crucial component utilized to implement a wide range of DSP tasks, including convolution, Fourier transform, discrete wavelet transforms (DWT), filtering and dithering, multimedia information processing, and more. A multiplier device includes a clock and reset buttons for more flexible operational control. Each digital signal processor constitutes a multiplier unit. A multiplier unit functions entirely autonomously from the central processing unit (CPU); consequently, the CPU is burdened with a significantly reduced amount of work. Since DSP algorithms must constantly carry out multiplication tasks, the employment of a high-speed multiplier to execute fast-speed filtering processes is vital. The previous multipliers had lots of weaknesses, such as high energy, low speed, and high area, because they implemented this necessary circuit based on traditional technology such as complementary metal-oxide semiconductor (CMOS) and very large-scale integration (VLSI). To solve all previous drawbacks in this necessary circuit, we can use nanotechnology, which directly affects the performance of the multiplier and can overcome all previous issues. One of the alternative nanotechnologies that can be used for designing digital circuits is quantum dot cellular automata, which is high speed, low area, and low power. Therefore, this manuscript suggests a quantum technology-based multiplier for DSP applications. In addition, some vital circuits, such as half adder, full adder, and ripple carry adder (RCA), are suggested for designing a multiplier. Moreover, a systolic array, accumulator, and multiply and accumulate (MAC) unit are proposed based on the quantum technology-based multiplier. Nonetheless, each of the suggested frameworks has a coplanar configuration without rotated cells. The suggested structure is developed and verified utilizing the QCADesigner 2.0.3 tools. The findings showed that all circuits have no complicated configuration, including a higher number of quantum cells, latency, and an optimum area. © 2024 Elsevier B.V.
Citation Count: 0
An Improved Evolutionary Method for Social Internet of Things Service Provisioning Based on Community Detection
(Institute of Electrical and Electronics Engineers Inc., 2024) Tawfeeq,B.A.; Rahmani,A.M.; Koochari,A.; Navimipour,N.J.
Social IoT (SIoT) refers to socializing in the Internet of Things (IoT), where things generate social relationships. Due to the development of objects and issues such as delayed response, slow search, and composite service process, distributed object service discovery, selection, and composition based on the social structure have become essential challenges in the SIoT. Therefore, it is necessary to provide an efficient method for evaluating the effectiveness of service discovery in identifying suitable devices to offer requested services and the best composition strategy for combining requested services. This paper presents a new community detection algorithm that detects IoT devices with social connections in the SIoT network to facilitate service discovery and composition by reducing search space. Additionally, it introduced a new service provisioning algorithm to optimize service discovery and composition, called An Improved Genetic Algorithm based on Community Detection (IGA-CD). Its effectiveness in detected communities is better than other methods in computation modularity, execution time, and cluster assignment quality methods by determining the network's ideal devices. Experimental results demonstrate the efficacy of the proposed algorithms, which outperform other approaches in terms of scalability, efficiency, and flexibility. The IGA-CD average execution time is 0.129 seconds, which proves its efficiency and faster composition. © 2013 IEEE.
Citation Count: 0
Machine/Deep learning techniques for multimedia security
(Institution of Engineering and Technology, 2024) Heidar,A.; Navimipour,N.J.; Azad,P.
Multimedia security based on Machine Learning (ML)/Deep Learning (DL) is a field of study that focuses on using ML/DL techniques to protect multimedia data such as images, videos, and audio from unauthorized access, manipulation, or theft. Developing and implementing algorithms and systems that use ML/DL techniques to detect and prevent security breaches in multimedia data is the main subject of this field. These systems use techniques like watermarking, encryption, and digital signature verification to protect multimedia data. The advantages of using ML/DL in multimedia security include improved accuracy, scalability, and automation. ML/DL algorithms can improve the accuracy of detecting security threats and help identify multimedia data vulnerabilities. Additionally, ML models can be scaled up to handle large amounts of multimedia data, making them helpful in protecting big datasets. Finally, ML/DL algorithms can automate the process of multimedia security, making it easier and more efficient to protect multimedia data. The disadvantages of using ML/DL in multimedia security include data availability, complexity, and black box models. ML and DL algorithms require large amounts of data to train the models, which can sometimes be challenging. Developing and implementing ML algorithms can also be complex, requiring specialized skills and knowledge. Finally, ML/DL models are often black box models, which means it can be difficult to understand how they make their decisions. This can be a challenge when explaining the decisions to stakeholders or auditors. Overall, multimedia security based on ML/DL is a promising area of research with many potential benefits. However, it also presents challenges that must be addressed to ensure the security and privacy of multimedia data. © The Institution of Engineering and Technology 2024. All rights reserved.
Citation Count: 1
A New Nano-Design of an Efficient Synchronous Full-Adder/Subtractor Based on Quantum-Dots
(ISRES Publishing, 2023) Kerestecioğlu, Feza; Navimipour,N.J.; Kerestecioglu,F.
Quantum-dot cellular automata (QCA), known as one of the alternative technologies of CMOS technology, promises to design digital circuits with extra low-power, extremely dense, and high-speed structures. Moreover, the next generation of digital systems will be used QCA as desired technology. In designing arithmetic circuits, efficient designs such as full-adder and full-subtractor can play a significant role. In addition, they are considering the most used structures in digital operations. Furthermore, full-adder and fullsubtractor are always effective parts of all complex and well-known circuits such as Arithmetic Logic Unit (ALU), Microprocessors, etc. This paper proposes low complexity and high-speed QCA coplanar synchronous full-adder/subtractor structures by applying formulations based on the Exclusive-OR gate to decrease energy consumption. The proposed design is simulated using QCADesigner 2.0.3. The simulation results confirm the efficiency of the proposed circuit. Moreover, comparative investigation indicates the superiority of proposed designs compared to state-of-the-art designs. Finally, the suggested QCA coplanar synchronous fulladder/subtractor shows 5.88% and 7.69% improvement in consumed cells relative to the best full adder and full subtractor, respectively. © 2023 Published by ISRES.