Browsing by Author "Seyedi, Saeid"

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A Fault-Tolerant Image Processor for Executing the Morphology Operations Based on a Nanoscale Technology
(Springer, 2023) Seyedi, Saeid; Jafari Navimipour, Nima; Navimipour, Nima Jafari
The morphology algorithms are an exciting field that provides a powerful and unified method applied to image and video processing applications. Also, they have many advantages to give manageable hardware implementations and are widely employed as parts of image processing techniques. On the other hand, Quantum-dot Cellular Automata (QCA) is a promising and novel nanotechnology that contains notable benefits against common technologies in diverse features like extremely small size, low energy loss, and high operation frequency. Besides, schematizing circuits with no info loss or fault-tolerant might be beneficial in reducing power wastage. In the present paper, we suggest a novel fault-tolerant procedure to execute the morphology operations in digital image processing based on QCA. The mentioned fault-tolerant schematization for executing the morphology operations in digital image processing is easy to build. It contains notably lower elements than Complementary Metal Oxide Semiconductor (CMOS) design. Implementation and testing of all circuits are achieved using the QCADesigner tool. The suggested fault-tolerant circuit for morphological dilation/erosion operation attains high fault-tolerant in all cases of defects.
Quantum-based serial-parallel multiplier circuit using an efficient nano-scale serial adder
(Soc Microelectronics, Electron Components Materials-midem, 2024) Jafari Navimipour, Nima; Jiang, Shuai; Seyedi, Saeid; Navimipour, Nima Jafari
Quantum dot cellular automata (QCA) is one of the newest nanotechnologies. The conventional complementary metal oxide semiconductor (CMOS) technology was superbly replaced by QCA technology. This method uses logic states to identify the positions of individual electrons rather than defining voltage levels. A wide range of optimization factors, including reduced power consumption, quick transitions, and an extraordinarily dense structure, are covered by QCA technology. On the other hand, the serialparallel multiplier (SPM) circuit is an important circuit by itself, and it is also very important in the design of larger circuits. This paper defines an optimized circuit of SPM circuit using QCA. It can integrate serial and parallel processing benefits altogether to increase efficiency and decrease computation time. Thus, all these mentioned advantages make this multiplier framework a crucial element in numerous applications, including complex arithmetic computations and signal processing. This research presents a new QCAbased SPM circuit to optimize the multiplier circuit's performance and enhance the overall design. The proposed framework is an amalgamation of highly performance architecture with efficient path planning. Other than that, the proposed QCA-based SPM circuit is based on the majority gate and 1-bit serial adder (BSA). BCA circuit has 34 cells and a 0.04 mu m2 area and uses 0.5 clock cycles. The outcomes showed the suggested QCA-based SPM circuit occupies a mere 0.28 mu m 2 area, requires 222 QCA cells, and demonstrates a latency of 1.25 clock cycles. This work contributes to the existing literature on QCA technology, also emphasizing its capabilities in advancing VLSI circuit layout via optimized performance.
A Space-Efficient Universal and Multi-Operative Reversible Gate Design Based on Quantum-Dots
(World Scientific Publ Co Pte Ltd, 2023) Seyedi, Saeid; Jafari Navimipour, Nima; Navimipour, Nima Jafari
Because of the high speed, low-power consumption, low latency and possible use at the atomic and molecular levels, Quantum-dot Cellular Automata (QCA) technology is one of the future nanoscale technologies that can replace the present transistor-based technology. For the purpose of creating QCA circuits, reversible logic can be regarded as an appropriate candidate. In this research, a new structure for multi-operative reversible designs is suggested. The Saeid Nima Gate (SNG), proposed in this research study, is a brand-new, incredibly effective, multi-operative, universal reversible gate implemented in QCA nanotechnology employing both majority and inverter gates. Reversible gates, also known as reversible logic gates, are gates that have n inputs and n outputs, which is an equal number of inputs and outputs. The amount of energy lost during computations will be reduced if the numbers of inputs and outputs are identical. The proposed gate is modified and reorganized to optimize further, employing exact QCA cell interaction. All fundamental logic gates are implemented using it to demonstrate the universality of the proposed SNG. Reversible logic has advanced, and as a result, our suggested solution has a lower quantum cost than previously reported systems. The suggested design is simulated using the QCADesigner-E tools.