dc.contributor.author | Ahmadpour, Seyed-Sajad | |
dc.contributor.author | Navimipour, Nima Jafari | |
dc.contributor.author | Kassa, Sankit | |
dc.contributor.author | Misra, Neeraj Kumar | |
dc.contributor.author | Yalcin, Senay | |
dc.date.accessioned | 2023-10-19T15:12:13Z | |
dc.date.available | 2023-10-19T15:12:13Z | |
dc.date.issued | 2023 | |
dc.identifier.issn | 0045-7906 | |
dc.identifier.issn | 1879-0755 | |
dc.identifier.uri | https://doi.org/10.1016/j.compeleceng.2023.108865 | |
dc.identifier.uri | https://hdl.handle.net/20.500.12469/5379 | |
dc.description.abstract | Quantum-dot cellular automata (QCA) has recently attracted significant notice thanks to their inherent ability to decrease energy dissipation and decreasing area, which is the primary need of digital circuits. However, the lack of resistance of QCA circuits under defects in previous works is a vital challenge affecting the stability of the circuit and output production. In addition, with the high defect rate in QCA, suggesting resistance and stable structures is critical. Furthermore, the 3input majority gate is a fundamental component of QCA circuits; therefore, improving this essential gate would enable the development of fault-tolerant circuits. This paper recommends a 3-input majority gate which is 100% fault-tolerant against single-cell omission defects. Moreover, the fundamental gates are introduced based on the proposed gate. In addition, an adder and a 1:2 decoder are also designed. Using QCADesigner 2.0.3 and QCAPro software, simulations of structures and analysis of power consumption are performed. | en_US |
dc.description.sponsorship | Ministry of Science and Technology (MOST) , Taiwan [MOST 110-2222-E-224- 002-MY3] | en_US |
dc.description.sponsorship | This work was supported in part by the Ministry of Science and Technology (MOST) , Taiwan, under Grant MOST 110-2222-E-224- 002-MY3. | en_US |
dc.language.iso | eng | en_US |
dc.publisher | Pergamon-Elsevier Science Ltd | en_US |
dc.relation.ispartof | Computers & Electrical Engineering | en_US |
dc.rights | info:eu-repo/semantics/closedAccess | en_US |
dc.subject | Full-Adder | En_Us |
dc.subject | Cellular-Automata | En_Us |
dc.subject | Full-Adder | en_US |
dc.subject | Decoder | en_US |
dc.subject | Error Probability Model | en_US |
dc.subject | Fault-tolerant 3-input majority gate (FTMG) | en_US |
dc.subject | Power Consumption | en_US |
dc.title | An ultra-efficient design of fault-tolerant 3-input majority gate (FTMG) with an error probability model based on quantum-dots | en_US |
dc.type | article | en_US |
dc.authorid | Misra, Neeraj Kumar/0000-0002-7907-0276 | |
dc.identifier.volume | 110 | en_US |
dc.department | N/A | en_US |
dc.identifier.wos | WOS:001048789300001 | en_US |
dc.identifier.doi | 10.1016/j.compeleceng.2023.108865 | en_US |
dc.identifier.scopus | 2-s2.0-85166229431 | en_US |
dc.institutionauthor | N/A | |
dc.relation.publicationcategory | Makale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanı | en_US |
dc.authorwosid | Misra, Neeraj Kumar/B-9442-2015 | |
dc.khas | 20231019-WoS | en_US |