Browsing by Author "Mosleh, Mohammad"

Now showing 1 - 11 of 11

Citation - WoS: 20
Citation - Scopus: 22
An efficient and energy-aware design of a novel nano-scale reversible adder using a quantum-based platform
(Elsevier, 2022) Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Mosleh, Mohammad; Bahar, Ali Newaz; Das, Jadav Chandra; De, Debashis; Yalcin, Senay
Quantum-dot cellular automata (QCA) is a domain coupling nano-technology that has drawn significant attention for less power consumption, area, and design overhead. It is able to achieve a high speed over the CMOS technology. Recently, the tendency to design reversible circuits has been expanding because of the reduction in energy dissipation. Hence, the QCA is a crucial candidate for reversible circuits in nano-technology. On the other hand, the addition operator is also considered one of the primary operations in digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, full-adders have become popular and extensively solve mathematical problems more efficiently and faster. They are one of the essential fundamental circuits in most digital processing circuits. Therefore, this article first suggests a novel reversible block called the RF-adder block. Then, an effective reversible adder design is proposed using the recommended reversible RF-adder block. The QCAPro and QCADesigner 2.0.3 tools were employed to assess the effectiveness of the suggested reversible full-adder. The outcomes of energy dissipation for the proposed circuit compared to the best previous structure at three different tunneling energy levels indicate a reduction in the power consumption by 45.55%, 38.82%, and 34.62%, respectively. (C) 2022 Elsevier B.V. All rights reserved.
Citation - WoS: 13
Citation - Scopus: 18
An Energy-Aware Nanoscale Design of Reversible Atomic Silicon Based on Miller Algorithm
(IEEE-Inst Electrical Electronics Engineers Inc, 2023) Ahmadpour, Seyed-Sajad; Jafari Navimipour, Nima; Bahar, Ali Nawaz; Mosleh, Mohammad; Yalcin, Senay
Area overhead and energy consumption continue to dominate the scalability issues of modern digital circuits. In this context, atomic silicon and reversible logic have emerged as suitable alternatives to address both issues. In this article, the authors propose novel nano-scale circuit design with low area and energy overheads using the same. In particular, the authors propose a reversible gate with Miller algorithm and atomic silicon technology. This article is extremely relevant in todays era, when the world is moving toward low area and low energy circuits for use in edge devices.
Citation - WoS: 8
Citation - Scopus: 12
Nano-Design of Ultra-Efficient Reversible Block Based on Quantum-Dot Cellular Automata
(Zhejiang Univ Press, 2023) Ahmadpour, Seyed Sajad; Navimipour, Nima Jafari; Mosleh, Mohammad; Yalcin, Senay
Reversible logic has recently gained significant interest due to its inherent ability to reduce energy dissipation, which is the primary need for low-power digital circuits. One of the newest areas of relevant study is reversible logic, which has applications in many areas, including nanotechnology, DNA computing, quantum computing, fault tolerance, and low-power complementary metal-oxide-semiconductor (CMOS). An electrical circuit is classified as reversible if it has an equal number of inputs and outputs, and a one-to-one relationship. A reversible circuit is conservative if the EXOR of the inputs and the EXOR of the outputs are equivalent. In addition, quantum-dot cellular automata (QCA) is one of the state-of-the-art approaches that can be used as an alternative to traditional technologies. Hence, we propose an efficient conservative gate with low power demand and high speed in this paper. First, we present a reversible gate called ANG (Ahmadpour Navimipour Gate). Then, two non-resistant QCA ANG and reversible fault-tolerant ANG structures are implemented in QCA technology. The suggested reversible gate is realized through the Miller algorithm. Subsequently, reversible fault-tolerant ANG is implemented by the 2DW clocking scheme. Furthermore, the power consumption of the suggested ANG is assessed under different energy ranges (0.5Ek, 1.0Ek, and 1.5Ek). Simulations of the structures and analysis of their power consumption are performed using QCADesigner 2.0.03 and QCAPro software. The proposed gate shows great improvements compared to recent designs.
Citation - WoS: 42
Citation - Scopus: 49
A Nano-Scale N-Bit Ripple Carry Adder Using an Optimized Xor Gate and Quantum-Dots Technology With Diminished Cells and Power Dissipation
(Elsevier, 2023) Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Mosleh, Mohammad; Bahar, Ali Newaz; Yalcin, Senay
In the nano-scale era, quantum-dot cellular automata (QCA) technology has become an appealing substitute for transistor-based technologies. QCA will be the preferred technology for developing the next generation of digital systems. On the other hand, the full-adder and ripple carry adder (RCA) are the crucial building blocks of complex circuits, the most used structures in digital operations systems, and a practical part of the most well-known complex circuits in QCA technology. In addition, this technology was used to design the full adder for several procedures, like multiplication, subtraction, and division. For this reason, the full adder is generally investigated as a central unit and microprocessor in developing QCA technology. Furthermore, most previous QCA-based adder structures have suffered from some drawbacks, such as a high number of cells, high energy consumption, the high number of gates, and the placement of inputs and outputs in a closed loop; hence, the implementation of an efficient adder with only one gate and a low number of cells, such as exclusive-OR (XOR) gate, can solve all previous problems. Therefore, in this paper, a significantly improved structure of 3-input XOR is suggested based on the promising QCA technology. In addition, a QCA clocking mechanism and explicit cell interaction form the foundation of the proposed QCA-based XOR gate configuration. This gate can be easily converted into an adder circuit while containing a small number of cells and being extremely compressed. The suggested QCA-based XOR design is focused on optimizing a single-bit adder using cellular interaction. The suggested single-bit adder contains 14 cells. Based on this adder, several different RCAs, such as 4, 8, 16, and 32-bit, are designed. The comparison of the proposed single-bit adder to the best coplanar and multi-layer ones shows a 51.72% and 36.36% reduction of cells, respectively. In addition, all suggested designs are verified through simulation using QCADesigner and QCAPro. Finally, many physical validations are provided to approve the functionality of the suggested XOR design.(c) 2023 Elsevier B.V. All rights reserved.
Citation - WoS: 23
Citation - Scopus: 31
A New Design of Parity Preserving Reversible Vedic Multiplier Targeting Emerging Quantum Circuits
(Wiley, 2023) Noorallahzadeh, Mojtaba; Mosleh, Mohammad; Ahmadpour, Seyed-Sajad; Pal, Jayanta; Sen, Bibhash
Reversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, Vedic mathematics, as a set of techniques sutras, has become popular and is extensively used to solve mathematical problems more efficiently and faster. This work proposes three PP reversible blocks, N-1, N-2, and N-3, which are used to develop a novel effective 2-bit PP reversible Vedic multiplier and 4-bit ripples carry adders (RCAs). Moreover, 2-bit Vedic multiplier and RCA are used to develop the 4-bit PP reversible Vedic multiplier. The proposed designs outperform the most relevant state-of-the-art structures in terms of garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Average savings of 22.37%, 35.44%, 35.44%, and 34.76%, and 17.76%, 26.60%, 24.52%, and 27.27% respectively, are observed for two-bit and four-bit PP reversible Vedic multipliers in terms of QC, GO, CI and GC as compared to previous works.
Citation - WoS: 1
Citation - Scopus: 1
A New Fault-Tolerance Majority Voter Circuit for Quantum-Based Nano-Scale Digital Systems
(Springer, 2025) Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Mosleh, Mohammad; Noorallahzadeh, Mojtaba; Kassa, Sankit; Ahmed, Suhaib
Quantum-dot cellular automata (QCA) technology has gained attention lately due to its ability to reduce energy dissipation and minimize circuit area. However, the existing research shows that a critical challenge arises from the lack of circuit resistance in QCA systems when confronted with defects. This issue directly impacts circuit stability and output generation. Moreover, the 3-input majority gate (MV3) is a foundational component within QCA circuits, making its improvement crucial for developing fault-tolerant circuits. One approach is to design MV3 that incorporates essential quantum cells within a single clock cycle. Thus, this paper presents a unique cellular structure for the MV3 gate, utilizing simple quantum cells. The proposed gate, comprising only twelve cells, serves as a building block for QCA circuits. It boasts several key features, including low power consumption, efficient output polarity (+/- 9.93e00-1), and high reliability. Furthermore, to show the efficiency of the suggested gate, it is employed in realizing a 2:1 multiplexer and a full adder/subtractor. Lastly, the proposed MV3 gate is utilized to develop a simultaneous multi-logic gate which is producing several vital digital circuits, such as AND, OR, NOT, NAND, Copy, Subtractor, and Adder. The circuits are designed using QCADesigner and QCAPro, with power estimation included in the process. The comparative analysis reveals that the proposed structures significantly enhance the trade-off between complexity, fault tolerance, and power consumption compared to previous designs.
Citation - WoS: 8
Citation - Scopus: 8
Novel efficient and scalable design of full-adder in atomic silicon dangling bonds (ASDB) technology
(Iop Publishing Ltd, 2023) Rasmi, Hadi; Mosleh, Mohammad; Navimipour, Nima Jafari; Kheyrandish, Mohammad
Atomic Silicon Dangling Bonds (ASDB) is an advanced emerging nanotechnology to replace CMOS technology; because it allows the designing of circuits with very high-speed and low-density. However, one of the most critical challenges in implementing circuits in ASDB nanotechnology is output stability and possible defects, such as DB omission, DB misalignment, and DB extra deposition, which can be overcome using a suitable designing pattern. Therefore, developing stable and robust structures is considered as one of essential topics in ASDB. This paper first proposes two novel and stable computing circuits, including a three-input majority voter (MV3) and three-input XOR (XOR3); based on triangular and rhombus patterns, respectively. Then, an efficient ASDB full-adder is designed using the suggested MV3 and XOR3 gates. Finally, two and four-bit ripple carry adders are developed using proposed full-adder. Simulation results indicate that the suggested MV3 and XOR3 are superior to previous designs, by more than 80%, 48%, and 9.5%, averagely; in terms of occupied area, energy, and occurrence, respectively. Moreover, the proposed gates are investigated against possible defects, and the results show high stability.
Citation - WoS: 28
Citation - Scopus: 31
Toward implementing robust quantum logic circuits using effectual fault-tolerant majority voter gate
(Elsevier, 2024) Negahdar, Kian; Mosleh, Mohammad; Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Shahrbanoonezhad, Alireza
Quantum -dot Cellular Automata (QCA) has emerged as a revolutionary technology for nano-scale computing circuits and a promising alternative to conventional transistor-based technologies. However, the susceptibility to defects during circuit synthesis is a pivotal challenge, undermining its potential. This study seeks to introduce an innovative and robust fault-tolerant 3 -input majority voter gate comprising 16 simple cells. The primary objective is to enhance the gate's resilience against two specific defects: one-cell omission and extra-cell deposition. Preliminary assessments indicate that the introduced gate achieves remarkable tolerance rates of 100% for one-cell omission and 89.47% for extra-cell deposition defects. A comprehensive evaluation is used based on the QCADesigner 2.0.3 simulator to validate the gate's performance, supplemented by physical proofs. Furthermore, leveraging the novel gate structure, this paper extends its application to the design of fault-tolerant flip-flops and multiplexer circuits. These building blocks are then employed to construct three distinct fault-tolerant sequential circuits.
Citation - Scopus: 2
Towards a Scalable and Efficient Full- Adder Structure in Atomic Silicon Dangling Band Technology
(Elsevier, 2025) Rasmi, Hadi; Mosleh, Mohammad; Navimipour, Nima Jafari; Kheyrandish, Mohammad
Atomic Silicon Dangling Bond (ASDB) is a promising new nanoscale technology for fabricating logic gates and digital circuits. This technology offers tremendous advantages, such as small size, high speed, and low power consumption. As science and technology progress, ASDB technology may eventually replace the current VLSI technology. This nanoscale technology is still in its early stages of development. Recently, many computing circuits, such as full-adder, have been designed. However, these circuits have a common fundamental problem; they consume a lot of energy and occupy a lot of area, which reduces the performance of complex circuits. This paper proposes a novel ASDB layout for designing an efficient full-adder circuit in ASDB technology. Moreover, a four-bit ASDB ripple carry adder(RCA) is designed using the proposed ASDB full-adder. The proposed ASDB fulladder not only improves the stability of the output but also surpasses the previous works, in terms of energy and accuracy,by 90% and 38%, respectively. Also, it has very favorable conditions in terms of occupied area and is resistant to DB misalignment defects.
Citation - WoS: 7
Citation - Scopus: 8
Towards Atomic Scale Quantum Dots in Silicon: an Ultra-Efficient and Robust Subtractor Using Proposed P-Shaped Pattern
(Ieee-inst Electrical Electronics Engineers inc, 2024) Rasmi, Hadi; Mosleh, Mohammad; Navimipour, Nima Jafari; Kheyrandish, Mohammad
Today, Complementary Metal-Oxide-Semiconductor (CMOS) technology faces critical challenges, such as power consumption and current leakage at the nanoscale. Therefore, Atomic Silicon Dangling Bond (ASDB) technology has been proposed as one of the best candidates to replace CMOS technology; due to its high-speed switching and low power consumption. Among the most important issues in ASDB nanotechnology, output stability and robustness against possible faults may be focused. This paper first introduces a novel P-shaped pattern in ASDB, for designing stable and robust primitive logic gates, including AND, NAND, OR, NOR and XOR. Then, two combinational circuits, half-subtractor and full-subtractor, are proposed by the proposed ASDB gates. The simulation results show high output stability as well as adequate robustness, against various defects obtained by the proposed designs; on average, they have improvements of more than 56% and 62%, against DB omission defects and extra cell deposition defects; respectively. Also, the results of the investigations show that the proposed circuits have been improved by 65%, 21% and 2%, in terms of occupied area, energy and occurrence, respectively; compared to the previous works.
Citation - WoS: 5
Citation - Scopus: 6
An Ultra Efficient 2:1 Multiplexer Using Bar-Shaped Pattern in Atomic Silicon Dangling Bond Technology
(Springer, 2024) Rasmi, Hadi; Mosleh, Mohammad; Navimipour, Nima Jafari; Kheyrandish, Mohammad
As CMOS technology approaches its physical and technical limits, alternative technologies such as nanotechnology or quantum computing are needed to overcome the challenges of lithography, transistor scaling, interconnects, and miniaturization. This article introduces a novel nanotechnology that uses atomic-scale silicon dangling bonds (ASDB) to create high-performance, low-power, nanoscale logic circuits. DBs are atoms that can form basic logic gates on a silicon surface using a scanning tunneling microscope device. ASDB can also be an alternative to the existing complementary metal oxide semiconductor (CMOS) technology. The article also proposes a new bar-shaped pattern to design gates and logic circuits with ASDB nano tecnolgoy. The bar-shaped pattern improves the reliability of the output, reduces the area and power consumption, and solves the problem of interatomic energy effects of ASDB. The article demonstrates the efficiency of the bar-shaped pattern by implementing two-input gates such as AND, NAND, OR, NOR, XOR, XNOR, and a 2:1 multiplexer with ASDB. The article also uses a powerful tool called SiQAD to simulate and verify the performance of the proposed structures with ASDB. According to the simulation results, the proposed logic gates are more energy efficient, stable, and compact than the previous structures. They consume 35% and 24.34% less energy and have 14.18% more stability, respectively.