High-Performance and Low-Power Quantum-Dot Multiply-Accumulate Design for Next-Generation Supercomputing Platforms

Abstract

The rapid growth of high-performance computing (HPC) and supercomputing applications necessitates hardware architectures that provide both high computational performance and strong energy efficiency under real-time and massively parallel workloads. However, conventional complementary metal-oxide semiconductor (CMOS) technologies face fundamental challenges, including excessive power consumption, leakage currents, and severe scaling limitations, which restrict their suitability for future exascale systems. To overcome these limitations, emerging nanotechnologies such as Quantum-dot Cellular Automata (QCA) have gained significant attention due to their ultra low-power consumption and high device density. In this work, we present a high-performance and low-power Quantum-Dot Multiply-Accumulate (Q-Dot MAC) unit, where MAC denotes a fundamental arithmetic operation combining multiplication and accumulation, extensively used in scientific computing, and signal processing. The proposed QCA-based architecture is specifically designed to satisfy the high-frequency (HF) operational demands of modern HPC environments, enabling sustained high-throughput computation. The main objective of this design is to realize a compact, energy-efficient, and physically stable MAC unit suitable for large-scale deployment in energy-constrained supercomputing platforms. Exploiting the inherent parallelism and high-density layout characteristics of QCA, the proposed MAC architecture efficiently executes key computational kernels required in HPC workloads, including large-scale matrix multiplication, convolution operations, and scientific simulations. The proposed QCA-based circuits demonstrate significant performance and area efficiency improvements compared with the best existing designs in the literature. Specifically, the half adder (HA) achieves a 20.51% reduction in cell count and a 25% reduction in area, and the complete MAC unit provides a 22.84% decrease in cell count, a 9.03% reduction in occupied area and a 14.25% in delay. These results confirm the efficiency and scalability of the proposed design. The low-area enables the integration of large arrays of MAC units, facilitating scalable systolic and Single Instruction Multiple Data (SIMD) architectures required in supercomputing environments.