Processor Design and Application of Futuristic

dc.authorscopusid 56405207500
dc.authorscopusid 57222637349
dc.authorscopusid 55823161800
dc.authorscopusid 57202686649
dc.authorscopusid 56912219900
dc.authorscopusid 59125628000
dc.authorwosid Bhoi, Bandan/N-2374-2017
dc.authorwosid Kassa, Sankit/G-5769-2015
dc.authorwosid Misra, Neeraj/B-9442-2015
dc.authorwosid Jafari Navimipour, Nima/Aaf-5662-2021
dc.contributor.author Jafari Navimipour, Nima
dc.contributor.author Pathak, Nirupma
dc.contributor.author Bhoi, Bandan Kumar
dc.contributor.author Ahmadpour, Seyed-Sajad
dc.contributor.author Kassa, Sankit R.
dc.contributor.author Navimipour, Nima Jafari
dc.contributor.other Computer Engineering
dc.date.accessioned 2025-05-15T18:39:21Z
dc.date.available 2025-05-15T18:39:21Z
dc.date.issued 2025
dc.department Kadir Has University en_US
dc.department-temp [Misra, Neeraj Kumar] VIT AP Univ, Sch Elect Engn, Amaravati 522237, Andhra Pradesh, India; [Pathak, Nirupma] Koneru Lakshmaiah Educ Fdn, Dept Comp Sci & Engn, Vaddeswaram 522502, Andhra Pradesh, India; [Bhoi, Bandan Kumar] Veer Surendra Sai Univ Technol, Dept Elect & Telecommun, Burla 768018, Odisha, India; [Ahmadpour, Seyed-Sajad] Kadir Has Univ, Fac Engn & Nat Sci, Dept Comp Engn, Istanbul, Turkiye; [Kassa, Sankit R.] Symbiosis Int Univ Pune, Symbiosis Inst Technol, Elect & Telecommun Dept, Pune, Maharashtra, India; [Navimipour, Nima Jafari] Natl Yunlin Univ Sci & Technol, Future Technol Res Ctr, Touliu 64002, Taiwan en_US
dc.description.abstract Many devices consist of low-power processor. Quantum-dot-cellular-automata (QCA) based processor designs provide enhanced performance compared with conventional metal-oxide-semiconductor (MOS) based processors. Nanocomputing-based processors are often energy-efficient. We have developed Nanotechnology QCA-based different subcomponents of processor such as 2-to-4 decoder, 3-to-8 decoder, Delay Flip-flop (D-FF), and sequence counter. A potential energy proof has been measured in the 2-to-4 decoder design. The synthesis approach algorithm has been presented for all designs. Further, the potential energy calculation results show for 2-to-4 decoder. According to the synthesis results 2-to-4 decoder has improved 82.3% cell count, 86% area, and 85% latency over previous work. Comparing the primitive results with the prior one, results improved by 64% and 76% in terms of cell count and area in the design of the 3-to-8 decoder. Among the different components of the processor is D-FF, which has an improvement of 66.37% in cell counts and 62.5% in area over the prior design. Primitive results have improved, including latency, cell count, and area, showing the proposed processor design is comparable to lowpower devices and high speed. In terms of balance power, the proposed subcomponent of the processor will benefit low power device. en_US
dc.description.woscitationindex Emerging Sources Citation Index
dc.identifier.doi 10.2298/FUEE2501163M
dc.identifier.endpage 186 en_US
dc.identifier.issn 0353-3670
dc.identifier.issn 2217-5997
dc.identifier.issue 1 en_US
dc.identifier.scopus 2-s2.0-105002062322
dc.identifier.scopusquality N/A
dc.identifier.startpage 163 en_US
dc.identifier.uri https://doi.org/10.2298/FUEE2501163M
dc.identifier.uri https://hdl.handle.net/20.500.12469/7314
dc.identifier.volume 38 en_US
dc.identifier.wos WOS:001460636600011
dc.identifier.wosquality N/A
dc.language.iso en en_US
dc.publisher Univ Nis en_US
dc.relation.publicationcategory Makale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanı en_US
dc.rights info:eu-repo/semantics/closedAccess en_US
dc.scopus.citedbyCount 0
dc.subject Qca en_US
dc.subject Computing en_US
dc.subject Processor en_US
dc.subject Sequence Counter en_US
dc.subject Decoder en_US
dc.subject Nanotechnology en_US
dc.subject Algorithm en_US
dc.subject Low Power en_US
dc.title Processor Design and Application of Futuristic en_US
dc.type Article en_US
dc.wos.citedbyCount 0
dspace.entity.type Publication
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