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dc.contributor.authorSoykan, Gürkan
dc.contributor.authorFlueck, Alexander J.
dc.contributor.authorDaǧ, Hasan
dc.date.accessioned2019-06-27T08:05:13Z
dc.date.available2019-06-27T08:05:13Z
dc.date.issued2010
dc.identifier.issn1827-6660
dc.identifier.urihttps://hdl.handle.net/20.500.12469/1046
dc.description.abstractOn-line transient stability analysis is a necessity for real-time power system control and security. Parallel processing is a natural technology for achieving real-time solution performance. This paper presents a parallel-in-space algorithm based on a multi-level partitioning scheme in a distributed memory cluster environment. The main aim of the research is to decrease the wallclock time of transient stability analysis of large scale power systems by leveraging open source software and commodity off the shelf hardware of a Linux PC cluster. The proposed solution algorithm focuses on speeding up the transient stability simulation by partitioning via METIS the linearized update solution process of the Very Dishonest Newton Method for solving the differential-algebraic equation system. Results are presented for two power systems: I) 3493 buses 844 generators 6689 branches and 2) 7935 buses 2135 generators 13624 branches. The simulations were run on a small Linux-cluster with a 100 Mbit/s ethernet interconnect which is cheaper than any specially constructed parallel computer. By tuning vertex weights the performance of the partition strategy can be improved relative to the no-weight case. The proposed method easily can be adapted by commercial packages and used in various parallel environments including multicore architectures with non-uniform memory access. Copyright (C) 2010 Praise Worthy Prize S.r.l. - All rights reserved.
dc.language.isoEnglish
dc.publisherPraise Worthy Prize Srl
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectDistributed Memory
dc.subjectMulti-level Partitioning
dc.subjectParallel Computing
dc.subjectSparse Linear Solver
dc.subjectTransient Stability Analysis
dc.titleDistributed Memory Parallel Transient Stability Analysis on a PC Cluster with Ethernet
dc.typeArticle
dc.identifier.startpage1053
dc.identifier.endpage1060
dc.relation.journalInternational Review Of Electrical Engineering-IREE
dc.identifier.issue3
dc.identifier.volume5
dc.identifier.wosWOS:000280934900029
dc.contributor.khasauthorDaǧ, Hasan


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