A synthesis tool for the multiplierless realization of FIR-based multirate DSP systems

Abstract

In this study a synthesis tool using a novel multirate folding technique which handles each FIR filter in a multirate DSP system as a single node is developed. A new architecture is presented for the multiplierless realization of a fold of multirate FIR filters. This synthesizer fully exploits the redundancies (i.e. `idle' and `missing' cycles) and common terms in multirate systems without sacrificing from overall system quality to produce multiplierless multirate systems. It also enables the usage of a single clock for all parts of the circuit.